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Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
FEATURES
* Two differential HSTL outputs * CLK0, CLK1 LVCMOS/LVTTL clock inputs * CLK0 and CLK1 can accept the following input levels: LVCMOS or LVTTL * Maximum output frequency: 350MHz * Part-to-part skew: 375ps (maximum) * Propagation delay: 1075ps (maximum) * VOH: 1.4V (maximum) * Full 3.3V and 2.5V operating supply voltage * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS85222-01 is a Dual LVCMOS / LVTTLto-Differential HSTL translator and a member of HiPerClockSTM the HiPerClocksTM family of High Performance Clock Solutions from ICS. The ICS85222-01 has two single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to HSTL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important.
IC S
BLOCK DIAGRAM
CLK0 Q0 nQ0 Q1 nQ1
PIN ASSIGNMENT
Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK0 CLK1 GND
CLK1
ICS85222-01
8-Lead SOIC 3.90mm x 4.92mm x 1.37mm body package M Package Top View
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REV. A NOVEMBER 15, 2005
Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
Type Output Output Power Input Input Pullup Pullup Description Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. Power supply ground. LVCMOS / LVTTL clock input. LVCMOS / LVTTL clock input.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5 6 7 Name Q0, nQ0 Q1, nQ1 GN D CLK1 CLK0
Power Positive supply pin. 8 VDD NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. NOTE: Unused output pairs must be terminated.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
4.6V -0.5V to VDD + 0.5V 50mA 100mA 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5% OR VDD = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDD IDD Parameter Positive Supply Voltage Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 2.375 Typical 3. 3 2.5 Maximum 3.465 2.625 35 Units V V mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5% OR VDD = 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 CLK0, CLK1 VDD = VIN = 3.465V VDD = VIN = 2.625V VDD = 3.465, VIN = 0V VDD = 2.625, VIN = 0V -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 1.3 5 Units V V A A
TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 3.3V5% OR VDD = 2.5V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing VDD = 3.3V5% VDD = 2.5V5% VDD = 3.3V5% VDD = 2.5V5% Test Conditions Minimum 1 0 0 0.6 0.45 Typical Maximum 1.4 0.4 0.55 1.4 1.4 Units V V V V V
NOTE 1: Outputs terminated with 50 to GND.
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REV. A NOVEMBER 15, 2005
Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
Test Conditions Minimum 700 20% to 80% 150MHz 150 < 250MHz 150 48 46 Typical Maximum 350 1075 375 800 52 54 Units MHz ps ps ps % %
TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V5%, TA = 0C TO 70C
Symbol fMAX tPD t sk(pp) tR / tF odc Parameter Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle
250 < 350MHz 45 55 % NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, VDD = 2.5V5%, TA = 0C TO 70C
Symbol fMAX tPD t sk(pp) tR / tF odc Parameter Output Frequency Propagation Delay; NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Output Rise/Fall Time Output Duty Cycle 20% to 80% 150MHz 150 48 700 Test Conditions Minimum Typical Maximum 350 1200 475 800 52 Units MHz ps ps ps %
150 < 350MHz 46 54 % NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A NOVEMBER 15, 2005
Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
PARAMETER MEASUREMENT INFORMATION
3.3V 5%
2.5V 5%
V DD
Qx
SCOPE
V DD
Qx
SCOPE
HSTL
nQx
HSTL
nQx
GND
GND
0V
0V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
PART 1 nQx CLK0, CLK1 nQ0, nQ1 Q0, Q1 tPD VDD 2 Qx PART 2 nQy Qy tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
nQ0, nQ1
80%
Q0, Q1
80% VSW I N G
t PW
t
PERIOD
Clock Outputs
20% tR tF
20%
odc =
t PW t PERIOD
x 100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
85222AM-01
OUTPUT RISE/FALL TIME
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Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
CLKx
V_REF
nCLKx
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. HSTL OUTPUT All unused LVHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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REV. A NOVEMBER 15, 2005
Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
physically located near the power pin. For ICS85222-01, the unused output need to be terminated.
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of ICS85222-01. In this example, the inputs are driven by 7 output LVCMOS drivers with series terminations. The decoupling capacitors should be
VDD=3.3V Zo = 50 Ohm Q1 Ro ~ 7 Ohm Zo = 50 Ohm 43 5 6 7 8 U1 GND CLK1 CLK0 VDD ICS85222-01 VDD=3.3V VDD=3.3V Q2 Zo = 50 Ohm Ro ~ 7 Ohm Zo = 50 Ohm R3 50 + R4 LVHSTL Input 50 C1 0.1u Zo = 50 Ohm nQ1 Q1 nQ0 Q0 4 3 2 1 Zo = 50 Ohm + R1 50 R2 50 LVHSTL Input -
R5 Driv er_LVCMOS
R6 Driv er_LVCMOS
43
FIGURE 2. ICS85222-01 HSTL BUFFER SCHEMATIC EXAMPLE
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REV. A NOVEMBER 15, 2005
Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85222-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85222-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 35mA = 121.3mW Power (outputs)MAX = 82.34mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 82.34mW = 164.68mW
Total Power_MAX (3.465V, with all outputs switching) = 121.3mW + 164.68mW = 285.98mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total device power dissipation (example calculation is in Section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.286W * 103.3C/W = 99.5C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE JA FOR 8-PIN SOIC, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 3.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
VDD
Q1
VOUT RL 50
FIGURE 3. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R ) * (V
L DD_MAX
-V
OH_MAX
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DD_MAX
-V
OL_MAX
Pd_H = (1.4V/50) * (3.465V - 1.4V) = 57.82mW Pd_L = (0.4V/50) * (3.465V - 0.4V) = 24.52mW Total Power Dissipation per output pair = Pd_H + Pd_L = 82.34mW
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REV. A NOVEMBER 15, 2005
Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR RELIABILITY INFORMATION
TABLE 6.
JAVS. AIR FLOW TABLE 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0 200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
153.3C/W 112.7C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85222-01 is: 443
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Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
FOR
PACKAGE OUTLINE - M SUFFIX
8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUM 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
Marking 5222A01 5222A01 5222A01L 5222A01L Package 8 Lead SOIC 8 Lead SOIC 8 Lead "Lead-Free" SOIC 8 Lead "Lead-Free" SOIC Shipping Package tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS85222AM-01 ICS85222AM-01T ICS85222AM-01LF ICS85222AM-01LFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85222AM-01
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REV. A NOVEMBER 15, 2005
Integrated Circuit Systems, Inc.
ICS85222-01
DUAL LVCMOS / LVTTL-TODIFFERENTIAL HSTL TRANSLATOR
REVISION HISTORY SHEET Description of Change Added Application Note, "Wiring the Differential Input to Accept Single Ended Levels". Ordering Information Table - added Lead-Free par t number. Added lead-free bullet. Added Recommendations for Unused Input and Output Pins. Corrected Power Considerations, Power Dissipation calculation. Ordering Information Table - added tape & reel quantity and lead-free note. Date 1/11/05
Rev A
Table
Page 6 11 1 6 8-9 12
T8 A T8
11/15/05
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